PDVL is an aspect-oriented and
transaction-level Programming, Design
and Verification
Language. The electronic
system level (ESL) language is inspired by SystemVerilog, SystemC and
many others, all the way back to HDLs from the
late 90's.
PDVL adds language construct to SystemVerilog. By doing that it adds
for example program paradigms
such as aspect and
transaction oriented programming. To name a few improvement over
existing languages, the method to define inverse transactions is added,
software sequences become integral part of static verification,
auto-abstraction during runtime is proposed and the paradigm of a
design hierarchy becomes only relevant when required. PDVL offers novel
solutions for state-of-the-art topics such as portable stimulus,
intelligent testbench generation and various other ESL methodologies.
My
paper "Deductive Formal Verification of Synthesizable,
Transaction-level Hardware Designs Using Coq" is now available: here.
The recodings of my
presentation “MRPHS:
Enabling Transaction-level Deductive Formal Verification Through
PDVL” at the 2024 Latch-Up Conference in Boston, USA (April
19-21) is available on youtube: here.
PDVL and automatic,
coverage-driven test generation:
I introduced PDVL at the IEEE Euromicro DSD Conference 2017:
T.Strauch, "An Aspect and Transaction Oriented Programming, Design and
Verification Language", IEEE Euromicro DSD 2017, Vienna, Austria, 30th
Aug.
- 1st Sep., pp. 30-39. http://ieeexplore.ieee.org/document/8049764/
A video was recorded at the ORConf 2017 in Hebden
Bridge, UK in September 2017, where I presented the basic concept of
PDVL to the open source
community: here.
The recodings of my
latest presentation “MRPHS:
Enabling Transaction-level Deductive Formal Verification Through
PDVL” at the 2024 Latch-Up Conference in Boston, USA (April
19-21) is available on youtube: here.
Currently I'm working on a documentation on how to use the language and
on an open source tool to support it. Stay tuned !